| AVS 59th Annual International Symposium and Exhibition | |
| Electronic Materials and Processing | Monday Sessions |
| Session EM+TF+OX+GR-MoA |
| Session: | High-k Dielectrics for MOSFETS II |
| Presenter: | C. Merckling, IMEC, Belgium |
| Authors: | C. Merckling, IMEC, Belgium A. Alian, IMEC, Belgium A. Firrincelli, IMEC, Belgium S. Jiang, IMEC, Belgium M. Cantoro, IMEC, Belgium J. Dekoster, IMEC, Belgium M. Caymax, IMEC, Belgium M. Heyns, IMEC, Belgium |
| Correspondent: | Click to Email |
The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based III-V semiconductors present the unique property of owning both high electrons (InSb) and holes (GaSb) mobilities, which triggered much of the interest in these III-Sb compounds for advanced CMOS. Moreover recent simulations have demonstrated that higher hole mobility could be found in strained III-antimonides compounds, suggesting the possibility of an all III-antimonide solution for full III-V based CMOS. In this work we studied the heteroepitaxy of 6.1 family semiconductors (GaSb, AlSb & InAs) on various III-V and Si substrates as well as the passivation of such semiconductors.
The relatively large lattice parameter of “6.1” semiconductors makes the growth and the integration on standard surfaces difficult. But is it possible to grow such semiconductors fully relaxed with low defect density due to the formation of a highly periodic array of 90º misfit dislocations at the III-Sb/substrate interface. In this contrbution both MBE and MOVPE growth techniques have been studied in order to propose novel integration scheme on Si substrate.
In a second part, we will focus on the passivation of these III-V semiconductors. Because III-V surfaces are very sensitive to oxygen compounds, this will generate the formation of native oxide. This undesirable interlayer will contribute aggressively to the high density of surface states within the energy band gap, resulting in Fermi level pinning which disturbs the basic III-V MOSFET-operation. In this context both ex-situ and in-situ Al2O3 high-κ gate dielectric deposition by standard ALD or MBD processes is reported. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors showed well-behaved C-V with relatively low Dit along the band gap. Such a Dit profile is promising for the future devices and suggests possibility to attain a low subthreshold swing.