AVS 59th Annual International Symposium and Exhibition
    Electronic Materials and Processing Friday Sessions
       Session EM+NS-FrM

Invited Paper EM+NS-FrM7
Scaling Silicide Contacts in Microlelectronics: At What Size will Material Characteristics affect Device Poperties ?

Friday, November 2, 2012, 10:20 am, Room 14

Session: Low-Resistance Contacts to Nanoelectronics
Presenter: C. Lavoie, IBM T.J. Watson Research Center
Correspondent: Click to Email
With the continued scaling of CMOS technology, the typical contact area to the source and drain of a CMOS device can now reach below 1000 nm2. At these nano-dimensions, typical intrinsic contact resistivities of 1x10-8 Ω- cm2, easily lead to resistances exceeding the KΩ solely for crossing the interface silicide-silicon. Such resistances are unacceptable as they dominate the overall resistance of a device. In an attempt to mitigate this increase in interfacial resistance with contact area reduction, much research has been performed concentrating on the tailoring of material properties of both the silicide and the semiconductor substrate as well as on the optimization of contact geometries and the advanced engineering of interfaces.As the size of the contact reaches dimensions that are similar or smaller than the typical microstructure of the expected poly crystalline material, some dramatic effects are to be anticipated. First, the presence of a single grain during the silicidation eliminates the typical dominant diffusion path: grain boundaries. As a result, phase nucleation and kinetics of growth can only proceed through the silicide bulk or the available interfaces. This will likely retard formation of the desired phases in the narrowest dimensions. Another expected disadvantage of very small contacts resides in the variability of the intrinsic contact resistance discussed above. It is accepted that the Schottky barrier height of a given silicide to a silicon substrate varies with substrate orientation. As a result, variation of crystal orientation from contact to contact may lead to dramatic effects on contact resistance. This orientation variation can originate from either a variation in silicide texture from contact to contact or a variation in device geometry (i.e. silicidation on Si(100), Si(110) or Si nanowire device depending on geometry).In this presentation, we will first explain how the importance of contact resistivity has caused a shift in contact engineering from yield and defect control towards the optimization of device performance. We will then describe some of the challenges involved in building arrays of nanostructures and characterizing them.