| AVS 59th Annual International Symposium and Exhibition | |
| Electronic Materials and Processing | Friday Sessions |
| Session EM+NS-FrM |
| Session: | Low-Resistance Contacts to Nanoelectronics |
| Presenter: | L. Caillard, University of Texas at Dallas |
| Authors: | L. Caillard, University of Texas at Dallas O. Seitz, University of Texas at Dallas P. Campbell, University of Texas at Dallas O. Pluchery, Université Pierre et Marie Curie, France Y.J. Chabal, University of Texas at Dallas |
| Correspondent: | Click to Email |
It has been suggested that the phenomenon of Coulomb blockade could be achieved by placing a metallic nanoparticle between two tunnel junctions. While the Coulomb blockade has been well established theoretically and demonstrated on metal substrates1, it is more challenging to observe on semiconductor surfaces due in part to the defective nature of the interfaces and to the depletion layer. We present an experimental study of two ultra small-capacitance normal tunnel junctions connected in series between the Si substrate and a STM tip. To achieve such a structure, we use an amine-terminated self-assembled monolayer (SAM) grafted on silicon (111) as the insulator layer, acting as a linker to attach gold nanoparticles on the surface. The SAM layer is grafted directly on oxide-free silicon through a Si-C bond formation using hydrosilylation reactions and is characterized by a low interface state density2. Moreover, this SAM layer provides a long-term passivation (weeks) of the interface that prevents oxidation of the substrate during Au nanoparticle deposition. The SAM quality is characterized using an extensive range of techniques, including in-situ IR spectroscopy, spectroscopic ellipsometry, X-ray photoelectron spectroscopy (XPS) and Atomic force microscopy (AFM). The second capacitance is formed by the gap between the gold nanoparticle and the tip of the Scanning tunneling microscope/spectroscope (STM/S). The current-voltage measurements have been performed in ultra high vacuum. Several parameters have been investigated: silicon doping level, sample temperature, and size of the gold nanoparticles (AuNPs), ranging from 1 to 15 nm. The junction is achieved by either grafting synthesized AuNPs or depositing evaporated gold directly on the SAM. Preliminary data confirm that coulomb staircases are observed under different conditions, mostly clearly for highly doped substrates at low temperature (10K). The steps width and height of these Coulomb staircases depend on particle size. These results are an important step toward future control for single electron transistor and flash memory applications.
[1] Zhang, H.; Yasutake, Y.; Shichibu, Y.; Teranishi, T.; Majima, Y., Tunneling resistance of double-barrier tunneling structures with an alkanethiol-protected Au nanoparticle. Phys. Rev. B, 72, (20) (2005)
[2] D. Aureau, Y. Varin, K. Roodenko, O. Seitz, O. Pluchery and Y. J. Chabal, Controlled Deposition of Gold Nanoparticles on Well-Defined Organic Monolayer Grafted on Silicon Surfaces. . Phys. Chem. C, 114 (33), pp 14180–14186 (2010)