As the DRAM technology evolved towards the sub 2x era, the need for high performance transistor grows higher for the DRAM peripheral transistors. The novel technologies such as embedded SiGe, high K gate oxide, or 3-dimensional transistor technologies are indispensible in a near future. Especially, to scale the gate oxide further and to meet the gate oxide leakage constraint at the same time, high K gate dielectrics should be adapted. For a successful application of high K dielectrics to DRAMs, it is essential to realize the effective work-function (EWF) for both n, pMOSFETs, where this EWF should be maintained even after huge back-end thermal budget of DRAM process. Therefore, so called ‘gate-first approach’ has been examined, i.e. LaO, or MgO capping layers for NMOS [1,2], and AlO capping layer, F implantation, and ion implantation on metal for PMOS [2,3], respectively. A SiGe channel has been also examined by many research groups [4-7]. When SiGe epitaxial layer is introduced to the PMOS channel, interface trap density (Dit) has been increased by order of magnitudes, which consequently results in the degradation of transistor performance and reliability [4]. To control this interface degradation, Si capping layers often deposited on the SiGe channels, which reduces the Vt gain that can be gained by SiGe only. In this research, SiGe selective epitaxial growth (SEG) condition has been set-up first, Si capping condition has been optimized by tuning growth temperature, process pressure, and Cl/Si ratio in a LPCVD chamber. The process pressure was precisely controlled to grow Si capping layer ‘selectively’ as well as to avoid SiGe migration. When we increased the process pressure, surface atomic mobility can be decreased, which effectively reduced SiGe migration. However, when the pressure is increased too high, resulting in growth rate too high, selective growth condition fails. HCl/SiH4 flow rates were also tuned to get a margin for selective growth condition. When introduced to DRAM peripheral transistors, a SiGe channel reduces PMOS Vth by 290 mV, and Si capped SiGe channel by 170 mV, respectively, which has good agreement with the expected value by Energy Band Simulation. This reduced Vt controllability could be recovered by increasing Ge content of SiGe channel. To conclude, the channel SiGe channel SEG process has been successfully applied for DRAM integration, and robust pMOSFET Vt tuner method was realized.