| AVS 58th Annual International Symposium and Exhibition | |
| Nanomanufacturing Science and Technology Focus Topic | Monday Sessions |
| Session NM+MS+NS+TF-MoM |
| Session: | ALD for Nanomanufacturing |
| Presenter: | Takuya Suzuki, Tokyo Institute of Technology and AIST, Japan |
| Authors: | T. Suzuki, Tokyo Institute of Technology and AIST, Japan M. Kouda, Tokyo Institute of Technology and AIST, Japan K. Kakushima, Tokyo Institute of Technology, Japan P. Ahmet, Tokyo Institute of Technology, Japan H. Iwai, Tokyo Institute of Technology, Japan T. Yasuda, AIST, Japan |
| Correspondent: | Click to Email |
La2O3 is one of the candidate materials for the next-generation high-k gate stacks because it can achieve sub-1 nm EOT by forming direct-contact La silicate with Si. There have been many ALD studies for La2O3, however, the performance of the MOSFETs incorporating ALD-La2O3 needs much improvement. Our previous studies using EB evaporation showed that capping the La2O3 dielectrics with an ultrathin layer of CeO2 or metallic Mg (~1 nm) effectively improved the channel mobility [1,2]. In this paper, we report fabrication of CeO2/La2O3 and MgO/La2O3 gate stacks by ALD/CVD for the first time, and demonstrate that these stacks show improved electrical properties (k value, channel mobility, etc.) as compared to single-layer ALD-La2O3.
The experiments were carried out using a multi-chamber ALD/CVD system which was capable of in-situ metallization and RTA. The CeO2/La2O3 and MgO/La2O3 gate stacks were formed on H-terminated Si(100) using Ce[OCEt2Me]4, La(iPrCp)3, and Mg(EtCp)2 metal sources. La2O3 and MgO films were formed by ALD using H2O as an oxidant. The ALD temperature was set at a relatively low temperature of 175°C in order to ensure the self-limiting growth [3]. CeO2 films were formed in the CVD mode via thermal decomposition of Ce[OCEt2Me]4 at 350oC. The gate electrodes were formed by sputtering of W. MOSFETs were fabricated by the gate-last process.
The effective k values for the CeO2(1nm)/La2O3(3nm) and MgO(0.8nm)/La2O3(4nm) stack capacitors were approximately 16, which was significantly larger than those for La silicate without any capping layer (k=10~12). The k-value improvement by the CeO2 capping is presumably due to the higher k value of CeO2 (~23), whereas the improvement by the MgO capping is ascribed to suppression of excessive La-silicate formation.
We have also found that the CeO2/La2O3 gate stack leads to excellent mobility characteristics. The mobility for the MOSFET with 1.43 nm EOT was 214 cm2/Vs at an effective field of 1.0 MV/cm, which was 85% of the Si universal mobility. The mobility improvement by the CeO2 capping is attributed to the reduced fixed-charge density, since Vth approached to the ideal values by the CeO2 capping. On the other hand, the MgO capping induced a negative shift in Vth and consistently degraded the mobility. These effects of ALD-MgO capping are qualitatively different from those observed for EB-evaporated Mg [2]. The mechanisms causing such a difference between EB evaporation and ALD are now under investigation.
This work was carried out in Leading Research Project for Development of Innovative Energy Conservation Technologies supported by NEDO.
References: [1] T. Koyanagi, et al., JJAP, 48, 05DC02 (2009); [2] M. Kouda, et al., 2009 VLSI Symp., p. 200; [3] K. Ozawa, et al.,2010 ICSICT, p. 932.