| AVS 58th Annual International Symposium and Exhibition | |
| Applied Surface Science Division | Tuesday Sessions |
| Session AS-TuP |
| Session: | Applied Surface Science Poster Session |
| Presenter: | Tyler Kent, University of California San Diego |
| Authors: | W. Melitz, University of California San Diego J. Shen, University of California San Diego T. Kent, University of California San Diego R. Droopad, Texas State University P.K. Hurley, Tyndall National Institute A.C. Kummel, University of California San Diego |
| Correspondent: | Click to Email |
Metal oxide semiconductor field effect transistors (MOSFETs) are the dominant logic device in modern electronics. Due to the challenges of scaling Si-MOSFETs alternative materials are being explored to improve device performance. III-V semiconductors are of interest for use in MOSFETs due to their high mobilities, but in order to make these devices competitive the semiconductor-oxide interface needs to have a low density of interfacial traps (Dit) in order to minimize subthreshold swings and also be atomically flat to allow high mobility at high field strengths. Current Si-MOSFET fabrication uses a gate last process which is an attractive method because it minimizes the gate oxides exposure to harsh processing conditions. In order for gate last processing to provide a nearly defect free semiconductor-oxide interface for surface channel devices, the channel surface must be in pristine condition before the oxide layer is deposited. In addition the oxide deposition process cannot introduce any defects. Recent advances show that a thin indium phosphide layer deposited on top of the InGaAs channel may provide superior electronic performance because the InGaAs/InP interface is defect-free and flat while the defects at the oxide/InP interface are less detrimental to device performance than the defects at the oxide/InGaAs interface.
In order to facilitate gate last processing of the InP/InGaAs channel stack, a four step process was investigated to clean and nucleate atomic layer deposition (ALD) of an InP/InGaAs surface. Samples were grown with an undoped 2 nm InP layer on ~1 µm InGaAs layer doped with 4 X 1018 cm-3 of Si on an InP wafer. Using in-situ atomic imaging (scanning tunneling microscopy), electronic measurements (scanning tunneling spectroscopy), and XPS a four step in-situ process was developed for converting an air-exposed InGaAs(100)-4x2 surface into a flat, electronically passivated, mono-layer nucleation template for ALD of gate oxides. The optimized process includes a small dose of atomic hydrogen, annealing to reduce surface roughness, TMA dosing to functionalize the surface, and a final annealing to induce a highly ordered ALD nucleation layer. Following atomic hydrogen cleaning at 380˚C and annealing at 470˚C, the surface was exposed to ~1 x 10-2 Torr of TMA at room temperature and annealed to 270˚C. The TMA induces a surface reconstruction consistent with a bulk like bonding configuration between the Al atoms and the surface P atoms. The TMA passivation layer has horizontal rows of DMA. The cleaning and nucleation process does not disrupt the InP surface thereby providing a path for further scaling of the InP layer and the gate oxide.