The optimization of phase change memory devices requires a compromise between reducing element sizes and maintaining data retention and reliability. The down-scaling of the memory cell size can be achieved only by a greater control of film deposition over non-planar structures than so far reached by physical vapor deposition techniques. A reduced cell size would allow lower programming currents, which lead to improved performances and lower costs. Metal organic chemical vapor deposition (MOCVD) is a very attractive method for growing layers because it enables the production of thin films with better conformality and composition control, including doping possibilities, and increased manufacturing throughput compared to sputtering techniques. Therefore, MOCVD is potentially attractive for the deposition of chalcogenide materials for phase change memory devices.

In this presentation recent advances in MOCVD of chalcogenide materials will be presented. Results will cover both the use of hot wire, liquid injection MOCVD and thermal, N2 based, MOCVD. The MOCVD growth is optimized both on flat SiO2/Si and patterned substrates. The deposition of Ge2Sb2Te5layers is achieved by thermal MOCVD thanks to the use of a thin seed layer of germanium. The obtained Ge-Sb-Te alloys exhibit up to 10 phase switching cycles upon laser irradiation. Better performances are achieved so far by hot wire MOCVD where the optical switching behavior is demonstrated to be comparable to the one of sputtered deposited Ge2Sb2Te5films of the same thickness. Moreover, prototype memory cells including Ge2Sb2Te5from hot wire MOCVD show promising performances.

 

Advances in material characterization will be also discussed. Since the switching of a memory device is driven by Joule heating, the exploration of new chalcogenide materials in terms of electrical performances cannot proceed without the knowledge of the thermal dependence of their fundamental properties, like thermal conductivity, electrical resistivity and crystallographic phase stability. The effect of reducing the cell size on the role played by the properties of the interfaces between the chalcogenide material and the other elements of the memory cell will be discussed. In particular, since most of the work performed in material characterization proceeds on flat, polycrystalline layers, special attention is devoted to the effects of size, preferential orientation and thin interfacial layers on the quantification of thermal and electrical properties as a function of temperature.