AVS 57th International Symposium & Exhibition | |
Thin Film | Tuesday Sessions |
Session TF1-TuM |
Session: | ALD: Dielectrics for Semiconductors |
Presenter: | C. Dubourdieu, CNRS and IBM Research |
Authors: | C. Dubourdieu, CNRS and IBM Research M.M. Frank, IBM T.J. Watson Research Center E. Cartier, IBM T.J. Watson Research Center J. Bruley, IBM T.J. Watson Research Center S.M. Rossnagel, IBM T.J. Watson Research Center A. Kellock, IBM Almaden Research Center V. Narayanan, IBM T.J. Watson Research Center |
Correspondent: | Click to Email |
A large part of the high-k dielectric stacks investigated for the replacement of the SiO2 or SixOyN gate oxide in metal-oxide-semiconductor (MOS) field-effect transistors consists of a Hf-based oxide or silicate deposited on top of an ultrathin interfacial SiO2 layer. We report here the formation of yttrium lanthanum silicate in direct contact with silicon for the fabrication of MOS capacitors with a resulting highly competitive equivalent oxide thickness (EOT) of 0.8nm. Such a low EOT is remarkable as it is obtained with a non Hf-based dielectric and following a high-temperature gate first route. This result is achieved by integrating Y2O3 films grown on buffer layers by a novel atomic layer deposition process that combines an original yttrium precursor and an innovative liquid injection source.
The growth of Y2O3 thin films by ALD from Y(EtCp)3 and water precursors will be presented. The yttrium precursor was introduced using a novel delivery scheme consisting of a pulsed injection system from Kemstream®. The control of the growth as a function of various process parameters (precursor supply time, water purging time, temperature) was investigated. Film stoichiometry was determined by Rutherford backscattering spectrometry. The reactivity of Y(EtCp)3 with water and the frontiers between ALD and CVD regimes will be discussed.
We describe MOS capacitors prepared from ALD-Y2O3 thin films deposited onto Si(p-type)/SiO2(0.8 nm)/La2O3 (1 nm) structures. The Y2O3 thickness ranges from 1.5 to 3.5 nm. The metal gate electrode consists of 10 nm TiN and implanted polysilicon on top. The complete stack undergoes a high-temperature RTA at 1000˚C for 5 s under N2 for dopant activation in the poly-Si, which simulates gate first process of CMOS transistor fabrication. Finally, a forming gas anneal is performed at 475˚C. The stack microstructure and composition were studied by transmission electron microscopy, electron loss spectroscopy and energy dispersive x-ray spectrometry. Interdiffusion reactions occur between SiO2, La2O3 and Y2O3 layers upon the RTA and result in an yttrium lanthanum silicate film in direct contact with Si. The elemental distribution within the silicate layer will be discussed. C-V and I-V were performed on 10x10 μm2 size capacitors in a frequency range of 1 kHz up to 300 kHz. EOTs as low as 0.8 nm were obtained for stacks with initially 3 nm Y2O3 deposited films. The leakage current density for such stacks is of 2.1x10-3 A/cm2 at -1V. The formation of silicate enables an appropriate VFB, which is tunable for nFET and pFET. Results obtained for stacks prepared from different buffer layers such as Al2O3 and HfO2 will also be discussed.