| AVS 57th International Symposium & Exhibition | |
| Electronic Materials and Processing | Wednesday Sessions |
| Session EM+SS-WeA |
| Session: | High-k Dielectrics for III-V Electronics |
| Presenter: | J.A. del Alamo, Massachusetts Institute of Technology |
| Correspondent: | Click to Email |
CMOS scaling is at the heart of the microelectronics revolution. The ability of Si CMOS to continue to scale down transistor size while delivering enhanced performance is becoming increasingly difficult with every generation of technology. For Moore’s law to reach beyond the limits of Si, a new channel material with a high carrier velocity is required. A promising family of materials for this is III-V compound semiconductors.
III-Vs are well known for their unique suitability for high frequency electronics. III-V-based integrated circuits are currently in use in a variety of communications and defense applications. The prospect of III-Vs entering the logic roadmap is tantalizing. This work reviews some of the critical issues.
The barrier for insertion of a new channel material into the CMOS roadmap is huge. Any new technology has to beat Si designs in performance at device footprints that allow the integration of billions of transistors on the same chip. In addition, cost-effective manufacturing must be realized.
To make this work, a III-V CMOS technology has to solve a number of challenging technical problems. The development of a gate stack that includes a high-K dielectric and yields a high-quality semiconductor interface with a III-V compound semiconductor is up there as one of the greatest and most fascinating problems in modern semiconductor technology. Recent research suggests that this is an eminently attainable goal. Transistor size scalability is also a major worry. Will it be possible to scale future III-V transistors to the required dimensions while preventing excessive short-channel effects and attaining the demanding parasitic resistance objective? This is a topic that will call for extensive experimental and simulation research. Fortunately, calibrated simulators today reproduce quite well the characteristics of 30 nm gate length III-V FETs and should be valuable in projecting to devices in the 10 nm range. If planar device designs are unsuitable, 3D designs might offer a viable path. Recent 3D device demonstrations with impressive characteristics give hope that this is a promising strategy. A future III-V CMOS technology will also have to “look and feel” as much as Si as possible. This calls for the formation of thin high-quality III-V layers on top of large Si wafers. In fact, depending on what emerges as the best option for the p-channel device, a major challenge in itself, two dissimilar materials might need to be integrated side by side in very close proximity on top of a Si wafer. These are all great problems that will require the coordinated attention of scientists and technologists with expertise in many different domains.