| AVS 57th International Symposium & Exhibition | |
| Electronic Materials and Processing | Wednesday Sessions |
| Session EM+SS-WeA |
| Session: | High-k Dielectrics for III-V Electronics |
| Presenter: | P. Ye, Purdue University |
| Correspondent: | Click to Email |
The principal obstacle to III-V compound semiconductors rivaling or exceeding the properties of Si electronics has been the lack of high-quality, thermodynamically stable insulators on III-V materials. For more than four decades, the research community has searched for suitable III-V compound semiconductor gate dielectrics or passivation layers. The literature testifies to the extent of this effort. The research on ALD approach is of particular interest, since the Si industry is getting familiar with ALD Hf-based dielectrics and this approach has the potential to become a manufacturable technology.
Using In-rich InGaAs as surface channel, high-performance inversion-mode high-k/III-V NMOSFETs have been demonstrated. By further improving on-state performance, such as maximum drain current Idss and peak transconductance Gm, the off-state performance or subthreshold characteristics need to be seriously evaluated for digital applications. In this talk, we review some new progresses on deep-submicron inversion-mode In0.7Ga0.3As NMOSFETs using 2.5 nm-5.0 nm ALD Al2O3 as high-k gate dielectrics. The Gm exceeds 1.1-1.3 mS/µm and starts to approach the values from InGaAs HEMTs. The scaling metrics, such as threshold voltage (VT), Ion/Ioff ratio, sub-threshold swing (S.S.), the drain induced barrier lowing (DIBL), as a function of the gate length from 150 nm to 250 nm are systematically studied. Retro-grade structure and halo-implantation are also applied to III-V MOSFET field to improve the off-state performance of InGaAs MOSFETs.In order to achieve better gate control capability, new structure design like FinFET demonstrated successfully in Si devices, is strongly needed for short-channel III-V MOSFETs. However, unlike Si, the dry etching of III-V semiconductor surface has been believed to be difficult and uncontrollable, especially related with surface damage and integration with high-k dielectrics. We also review some results on the first experimental demonstration of inversion-mode In0.53Ga0.37As tri-gate FinFET using damage-free etching and ALD Al2O3 as gate dielectric. The SCE is greatly suppressed.
The work is in close collaborations with Y.Q. Wu, Y. Xuan, J.J. Gu and M. Xu. We also would like to thank valuable discussions with D. Antoniadis, M.S. Lundstrom, R.M. Wallace, K.K. Ng, M. Hong, and J. Woodall.