Paper TF-WeA7
Study of Silicon Strain in Shallow Trench Isolation

Wednesday, November 11, 2009, 4:00 pm, Room B4

Generation of strain in a silicon channel has been successfully used to increase performance of state of the art CMOS devices. The most studied methods are embedded silicon germanium, stress liners and stress memorization techniques. However, there have been relatively few studies of the effect of thin film dielectric materials in the Shallow Trench Isolation (STI) area on silicon strain.

Raman spectroscopy has been used as a primary tool to measure silicon strain on a variety of STI structures. Different STI dielectric gap fill materials have been evaluated including high density plasma CVD, sub-atmospheric CVD and spin-on glass based oxide thin films. It has been shown that both intrinsic stress of thin film dielectric material and STI structure type affect strain in silicon. Ways of introducing new dielectric gap fill materials and generating high stress in STI are discussed including the effect of the STI CVD liner material on Si strain.

Advantages and limitations of Raman based strain metrology in the semiconductor industry are delineated. Raman spectroscopy showed much better sensitivity to Si strain compared to TEM based strain measurement techniques.

The findings have been confirmed electrically on CMOS devices with tensile and compressive strain in STI region. Substantial improvement in pFET transistor performance has been demonstrated for devices with tensile dielectric in STI.