| AVS 56th International Symposium & Exhibition | |
| Thin Film | Thursday Sessions |
| Session TF-ThA |
| Session: | Next Generation Processing |
| Presenter: | L.G. Villanueva, EPFL, Switzerland |
| Authors: | L.G. Villanueva, EPFL, Switzerland O. Vazquez-Mena, EPFL, Switzerland J. Montserrat, IMB-CNM-CSIC, Spain K. Sidler, EPFL, Switzerland V. Savu, EPFL, Switzerland J. Bausells, IMB-CNM-CSIC, Spain J. Brugger, EPFL, Switzerland |
| Correspondent: | Click to Email |
The fabrication of micro and nano devices using standard processing techniques is mainly based on the pattern transfer of designs onto a substrate. These standard techniques use pre-patterned resists that selectively expose certain parts of the substrate either to material deposition or implantation or to an etching process. The use of resist processes implies the coating, exposure, development and removal of the resist and also imposes certain restrictions regarding the materials and substrates to pattern (e.g. only flat substrates are acceptable). An alternative to resist-based processes is the use of stencil lithography (SL), which relies on the use of a shadow mask membrane, and has already been proved to achieve sub-micrometer resolution for metallization, and more recently for direct-etching and ion-implantation. In this abstract we present the combination of the three mentioned techniques to fabricate Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET).
The proposed fabrication process flow of the MOSFETs follows the basic stages (Figure 1 in supplementary information) starting with a 100 mm diameter p-doped silicon wafer in which the n-doped regions for Source-Drain definition are implanted through stencil. Subsequently, the gate oxide is grown in a process that also activates the impurities in the lattice. Contacts for Source and Drain are opened in the oxide by means of dry etching through stencil and, finally, metal pads are deposited through stencil. All the stencils used were fabricated using standard microfabrication techniques (i.e. resist based processes) in 100 mm diameter wafers. However, for better compatibility with the processing equipment during MOSFET fabrication, the wafers were cleaved and the stencils were used in chip size.
Different designs were included in the fabrication: resistors, transistors and NOR gates. In addition, to demonstrate the capability of SL to pattern non conventional substrates, the transistors were fabricated not only on flat substrates, but also at the bottom of pre-patterned steps of 40 µm and 100 µm (Figure 2 of supplementary information).
The characterization shows that resistors have a linear I-V behavior. The square resistance decreases with the gap as expected (Figure 3, supplementary information). In addition, transistors also show the expected behavior (Figure 4, supplementary information), with a well defined saturation region.
The presented technique proposes a new concept for the fabrication of electronic devices, allowing the fabrication of structures on pre-patterned surfaces with resolutions close to the micrometer, which can be of great utility for some specific applications.