AVS 53rd International Symposium
    Nanometer-scale Science and Technology Thursday Sessions
       Session NS-ThA

Paper NS-ThA1
Controlled Chemical Mechanical Polishing of Polysilicon and Silicon-Dioxide for Nanostructures

Thursday, November 16, 2006, 2:00 pm, Room 2016

Session: Nanoscale Material Processing
Presenter: V. Joshi, University of Notre Dame
Authors: V. Joshi, University of Notre Dame
A.O. Orlov, University of Notre Dame
G.L. Snider, University of Notre Dame
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In this paper, we report experimental results of silicon dioxide (SiO@sub 2@) and polysilicon chemical mechanical polishing (CMP) to produce nanoscale features with very smooth surfaces. The sizes of the features polished ranged from 20 to 500 nm. Nanostructures were defined by e-beam lithography and reactive ion etching (RIE). For polysilicon polishing, the nanostructures were defined in ZEP-520A (positive tone e-beam resist) and pattern was transferred to the oxide substrate through RIE (CHF@sub 3@/O@sub 2@) plasma. These etched nanostructures (70 nm deep trenches) were conformally filled with LPCVD polysilicon, and polished using a Logitech CDP system. The slurry used was Semi-Sperse P1000 from Cabot Microelectronics. Similarly for oxide CMP study, nanostructures were patterned on Si substrate using HSQ (negative tone e-beam resist) as the etch mask. These nanostructures in Si (~100 nm height) were covered with thick layer of PECVD SiO@sub 2@. Polishing was done to planarize the sample and expose the Si structures. CMP-1150 slurry from Ekctech was used for oxide CMP. The polished structures were studied using SEM (cross-sections) and AFM (surface). We report controllable CMP to realize ~20 nm thick layers after polishing. The RMS roughness of the polished surfaces was ~ 0.3 nm. Better control of the CMP process (2 nm/min removal rate) was demonstrated by using diluted slurry or pure DI water as the CMP slurry.