AVS 53rd International Symposium
    Electronic Materials and Processing Thursday Sessions
       Session EM2-ThA

Invited Paper EM2-ThA5
Combining Ferroelectric Oxides and Semiconductors for Smart Transistors

Thursday, November 16, 2006, 3:20 pm, Room 2003

Session: Electronic Properties of High-k Dielectrics, Ferroelectrics, and Their Interfaces
Presenter: J. Singh, University of Michigan
Correspondent: Click to Email
Semiconductors have been exploited for decades in creating intelligent devices. However, oxides and other insulators have at most provided passive roles as insulators or passivation layers. Recent work has been showing that it is possible to grow reasonable quality oxide-semiconductor interfaces. Is it possible to have oxide-semiconductor heterostrucutres where the best of semiconductors and the best of oxides (polar charge, tailorable polarization, large bandgap, tailorable dielectric response etc.) can be exploited? There are a large number of potential material systems that have polar character which are not (yet) considered to be relevant to semiconductor technology. These include ferroelectrics, pyroelectrics and piezoelectric materials where polar charges as high as 1 electron per surface atom can be present.For these structures to make an impact a number of parameters need to be evaluated. These include: (i) band lineup; (ii) polarization vs. thickness; (iii) dielectric response vs. thickness; (iv) and most importantly defect structures. In absence of all this knowledge it is still possible to examine the potential of new heterostructures that exploit polar materials. Theoretical studies can provide estimates of the level of perfection needed to make new devices possible. Polarization differences at interfaces can be used to create very large band bending which in turn can be used to induce electron (hole) gas, create tunnel junctions, cause lateral as well as vertical band engineering. Most interestingly these structures can result in smart FETs which have high transconductance and respond not only to gate bias but to pressure, temperature variations, etc. At this point in time these structures can serve as test cases to examine the potential of oxide-semiconductor structures and to see if the interfaces can reach the needed quality for functional devices.