AVS 53rd International Symposium
    Electronic Materials and Processing Tuesday Sessions
       Session EM-TuA

Invited Paper EM-TuA3
SiC/SiO@sub2@ Interface and Near Interface Traps in SiC Based MOSFETs

Tuesday, November 14, 2006, 2:40 pm, Room 2003

Session: Materials for Power Electronics
Presenter: P.M. Lenahan, Penn State University
Authors: P.M. Lenahan, Penn State University
M.S. Dautrich, Penn State University
A.J. Lelis, US Army Research Labs
Correspondent: Click to Email
Considerable progress has been made in the development of metal oxide semiconductor (MOS) field effect transistors (MOSFETs) based on SiC/SiO@sub2@ structures.@footnote 1@ The most promising devices utilize the 4H SiC polytype. Although, SiC/SiO@sub2@ MOS technology holds great promise in high-power and high-temperature applications, at the present time, SiC based devices exhibit mediocre performance. The device performance is limited, in large part, by trapping centers at and very near the SiC/SiO@sub2@ interface. This presentation will deal with electron spin resonance (ESR) and conventional electronic measurements of SiC MOS devices which provide some understanding of the physical and chemical nature of these performance limiting traps.@footnote 2@ Most of the ESR results have been obtained through very sensitive electrically detected magnetic resonance (EDMR) measurements on fully processed transistors via spin dependent recombination (SDR). These measurements clearly demonstrate fundamental differences between the physical nature of the defects which limit the performance of conventional Si/SiO@sub2@ based MOSFETs and current day SiC- based MOSFETs. In Si/SiO@sub2@ MOSFETs, for example, most of the observed "interface traps" are located precisely at the semiconductor/insulator boundary. In SiC-base devices this is not the case. The magnetic resonance results clearly demonstrate the presence of fairly high densities of deep level centers which are intrinsic in nature. These defects extend below the SiC/SiO@sub2@ interface into the SiC. We argue that the dominating interface/near interface defect in 4H SiC transistors involves a vacancy center. The concentration and physical distribution of this center depends strongly upon processing variables. @FootnoteText@ @footnote 1@ J.C. Zolper and M. Skowronski, MRS Bulletin 30.4 (Apr 2005) p273-275@footnote 2@ M.S. Dautrich, P.M. Lenahan, and A.J. Lelis: To Be Published, Mater. Sci. Forum 2006.