AVS 53rd International Symposium
    Electronic Materials and Processing Thursday Sessions
       Session EM-ThP

Paper EM-ThP32
Yield improvement of 0.13 µm Cu/Low-k Dual Damascene Interconnection by Organic Cleaning Process

Thursday, November 16, 2006, 5:30 pm, Room 3rd Floor Lobby

Session: Electronic Materials and Processing Poster Session
Presenter: H.K. Lee, Chung-Ang University, Korea
Authors: H.K. Lee, Chung-Ang University, Korea
N.H. Kim, Chosun University, Korea
S.Y. Kim, DongbuAnam Semiconductor Inc., Korea
C.I. Kim, Chung-Ang University, Korea
E.G. Chang, Chung-Ang University, Korea
Correspondent: Click to Email
Cu/low-k dielectrics are required to reduce RC delay and parasitic capacitance of the back-end-of-line (BEOL) interconnection. Integration of Cu/low-k dielectrics for BEOL interconnection in the 0.13 µm technology has gained wide acceptance in the microelectronics industry in recent years. In this paper, we discuss the process integration issues of the 0.13 µm Cu/low-k (Black Diamond) dual damascene integration for SRAM device yield. The same scheme of 0.13 µm Cu/ fluorinated silicate glass (FSG) based device was used for full process in making low-k based device. Black diamond was used as a low-k material with a dielectric constant of 2.95. To reduce the damage of low-k and improve the yield of low-k based device, H@sub 2@O ashing, organic cleaning, and low down pressure in chemical mechanical planarization (CMP) were selected for the study. Specially, the organic cleaning process after ashing process is very effective on the removal of organic residues in via and trench, and surface contaminant. There is an increase of 40% SRAM device yield, compared to low-k based device which is uncleaned after ashing process. As a result, we successfully integrated 0.13 µm Cu/low-k (Black Diamond) dual damascene interconnection with excellent yield performance after process improvement of organic cleaning.