AVS 53rd International Symposium
    Electronic Materials and Processing Thursday Sessions
       Session EM-ThP

Paper EM-ThP29
Inspection and Analysis of Voiding Defects in Copper Interconnects on a Test Wafer

Thursday, November 16, 2006, 5:30 pm, Room 3rd Floor Lobby

Session: Electronic Materials and Processing Poster Session
Presenter: S. Suzuki, Hitachi High-Technologies Corporation, Japan
Authors: S. Suzuki, Hitachi High-Technologies Corporation, Japan
Y. Nakano, Hitachi High-Technologies Corporation, Japan
K. Umemura, Hitachi High-Technologies Corporation, Japan
T. Sato, Hitachi High-Technologies Corporation, Japan
Correspondent: Click to Email
For improvement of yield of LSI, it is necessary to use the analysis system that consists of inspection of defects of a wafer, analysis of defects and countermeasures. Voiding of Cu interconnects affect yield and reliability of ULSI, therefore it is so useful to detect efficiently voids of Cu layer in the manufacturing process. In this study, we have investigated the efficient analysis technique of voids by using the system. Void and etching stopped defects were intentionally on a 200mm wafer with 160nm diameter Cu via pattern made by typical single damascene process. Inspection of the wafer was done by electron beam (EB) inspection and optical inspection equipments, for cross section analysis samples from the wafer were made by focused ion beam (FIB) equipment, and defects were observed by scanning transmission electron microscope (STEM) with energy dispersive X-ray spectroscopy (EDS).The 2 types of defects (called one gray defect, the other dark defect), which contrast were different, were detected by EB inspection. The STEM results confirmed that gray defect was a void defect; dark one was an etching stopped defect. By cross section observation of 10 defects, there is a coincidence that all gray defects were voids and all dark were etching stopped. In the gray defect Cu was partially missing and only Ta/TaN layer remained, and it was estimated that voiding was finally occurred at annealing step of process because Cu seed layer also was missing. We are able to explain that difference of contrast is caused difference of electrical current through via, which depends on resistivity, for example a single via with 180nm height void is 10 times resistivity of that without void by rough calculation. In addition, we tried to quantify SEM image of the 2 types of defects, and actually measure resistivity of via by means of electrical probing equipment with SEM. Finally we find that EB inspection and quantification of SEM image is an efficient method to detect and classify defects.