The use of new materials for gate dielectric and metal gates, the very core of an FET, poses serious materials challenges. Most of the problems are first encountered by electrical characterization, however it is often a matter of structural characterization to understand and solve the problems. Typical difficulties involve capacitance loss, poor mobility, and incorrect device operating thresholds. This talk will highlight how analytical capabilities can guide our thinking on these problems using techniques such as medium energy ion scattering (MEIS), x-ray photoemission spectroscopy (XPS) and other methods. Generally, capacitance loss can be traced to growth of interfacial oxide, which can be detected by numerous methods. Finding the source of excess oxygen may involve detailed process learning and strict control of oxygen contamination throughout the gate stack. Mobility degradation is a more elusive problem, since many factors can come into play. I will show one example where depth profiling in HfSiOx using MEIS provides crucial information: non-uniform Si content correlates with poor performance. Perhaps the most difficult analytical challenge is posed by threshold voltage characteristics, which are dominated by dielectric charge and work function alterations. So far, we can only indirectly measure the problem through band offset measurements without directly sensing the defects responsible for the problem. There is a tremendous opportunity for materials characterization to resolve the problems faced by the microelectronics industry. This talk will outline some of the ways we can meet this challenge.