AVS 52nd International Symposium
    Nanometer-Scale Science and Technology Tuesday Sessions
       Session NS-TuP

Paper NS-TuP21
Electrical Properties of a Silicon Nanocrystal Embedded in a SiO2 Layer

Tuesday, November 1, 2005, 4:00 pm, Room Exhibit Hall C&D

Session: Nanometer Scale Science and Technology Poster Session
Presenter: J.M. Son, Myongji University, Korea
Authors: J.M. Son, Myongji University, Korea
J.M. Kim, Myongji University, Korea
S.Y. Seong, Myongji University, Korea
Y. Khang, Samsung Advanced Institute of Technology, Korea
B.K. Kim, Samsung Advanced Institute of Technology, Korea
K.S. Seol, Samsung Advanced Institute of Technology, Korea
E.H. Lee, Samsung Advanced Institute of Technology, Korea
J. Lee, Samsung Advanced Institute of Technology, Korea
Y.S. Kim, Myongji University, Korea
C.J. Kang, Myongji University, Korea
Correspondent: Click to Email
Si nanocrystal (Si NC) based device is a promising candidate for the future non-volatile memory. It is advantageous in terms of low power consumption, small device size, excellent stress induced leakage current (SILC) immunity and better retention. Since the characteristics of Si NCs memories in which the conventional poly-Si floating gate is replaced by an array of Si NCs is affected by the electrical properties of each NC, the isolation of Si NCs plays an important role. The Si NC samples produced by laser ablation method were followed by sharpening oxidation steps. In these steps Si NCs are capped with a thin oxide layer of 1~2nm thickness for isolation and the size control. It also affects the interface states of NCs, resulting in the change of electrical properties. To find out this effect, we observed localized electrical properties of a capped Si NC by scanning probe microscopy (SPM). And these results were compared with C-V characteristics of the conventional MOS capacitor structure.