AVS 52nd International Symposium
    Manufacturing Science and Technology Tuesday Sessions
       Session MS-TuP

Paper MS-TuP2
The Dependence of Power Trench MOSFET Processes on Wafer Thickness

Tuesday, November 1, 2005, 4:00 pm, Room Exhibit Hall C&D

Session: Topics in Advanced Manufacturing Poster Session
Presenter: M. Daggubati, Fairchild Semiconductor
Authors: M. Daggubati, Fairchild Semiconductor
G. Sim, Fairchild Semiconductor
D. Long, Fairchild Semiconductor
H. Paravi, Fairchild Semiconductor
Q. Wang, Fairchild Semiconductor
Correspondent: Click to Email
The dependence of trench MOSFET processes on wafer thickness has been studied in detail. In the photolithography process, it was found that the photoresist thickness decreased 30Å when wafer thickness decreased from 675µm to 508µm. This is due to the fact that thinner wafer has less thermal dissipation time i.e. Thinner wafer dissipates heat better and heats up quicker than thicker wafer during baking resulting in more evaporation of the photoresist solvent. Unless compensated for, this change in resist thickness adds to process variation affecting critical dimension (CD) and trench depth control. In the silicidation process, after the rapid thermal processing (RTP), the thinner wafers exhibited a lower resistance and higher silicide stress of 3.23E+10 dynes/cm@super 2@ (compared to thick wafers of 4.60E+09 dynes/cm@super 2@) at the source contact due to the reasons mentioned above. Also, the stress is more uniform across the wafer. The Ti/Si reaction is time and temperature dependent. Higher temperature results in more silicide and the reaction creates a volume reduction that induces stress. The silicide layers on the Si wafers have been analyzed using Z-constrast imaging in transmission electron microscopy (TEM) and energy dispersive x-ray (EDX) profiling techniques. Both Z-contrast imaging and EDX profiling revealed a 50 nm thick TiSi layer on the top of TiSi@sub 2@ layer for the thicker wafers. Whereas, no TiSi layer was found in thinner wafers, but Ti-enrichment in the outer part was sometimes observed. The TiSi layer, especially when it's continuous, can modify the electrical property of the devices. The formation of TiSi layer could be attributed to insufficient Si atoms diffused to the outer layer. Higher temperatures in thinner wafers seem to assist in the removal of this TiSi layer.