AVS 52nd International Symposium
    MEMS and NEMS Tuesday Sessions
       Session MN-TuM

Paper MN-TuM8
Copper Electroplating to Fill Blind Vias for 3D Integration

Tuesday, November 1, 2005, 10:40 am, Room 207

Session: Micro and Nano Fabrication Techniques for MEMS & NEMS
Presenter: S. Spiesshoefer, University of Arkansas
Authors: S. Spiesshoefer, University of Arkansas
S. Polamreddy, University of Arkansas
R. Figueroa, University of Arkansas
J. Patel, University of Arkansas
T. Lam, University of Arkansas
L. Cai, University of Arkansas
S. Burkett, University of Arkansas
L. Schaper, University of Arkansas
Correspondent: Click to Email
The continued demand for lower cost electronic products with decreased size, higher performance and increased functionality require improvements in the system level integration of logic, memory, and other functional integrated circuits. The formation of vertical interconnects in silicon may be one approach to provide this integration. This method involves stacking of individual die to form a highly interconnected 3D structure. One way to create an efficient 3D stack is to place electrically conductive vias through the body of the silicon to bring the connections from top to bottom. Copper is the metal used to fill the through silicon via (TSV) structure because of the high conductivity and the common use in multilevel wiring. A process will be described in this paper to electroplate copper into small diameter (5-10 µm) vias of aspect ratio > 3. The objective of this project is to develop an electroplating process to obtain a void-free copper filled blind via. Prior to plating, vias are formed by both reactive ion etch (RIE) and deep RIE processes. The resulting via profile varies depending on the etch process chosen. Vias are lined with insulation, barrier, and seed films. The insulation, SiO@sub2@, is deposited by plasma enhanced chemical vapor deposition (PECVD) while the barrier (TaN) and Cu seed layers are deposited by sputtering. A complete and conformal copper seed layer is essential for the electroplating process. A combination of three electroplating techniques is used in this study. They consist of optimized bath composition (additive control), fountain plating, and reverse pulse plating. The goal during electroplating is to achieve a bottom-up fill, also referred to as a super fill. The process will be described that results in void-free electroplating to fill an array of blind vias as well as the related processing issues.