Future generations of silicon devices will require approaches beyond the conventional in terms of both fabrication and characterization. In particular, instead of bulk Si, most devices will use silicon-on-insulator (SOI) or variants, such as strained-Si-on-insulator (sSOI), SiGe-on-insulator (SGOI), Si-on sapphire (SOS), and so forth, where in all cases a very thin crystalline layer of Si or SiGe is bound to an oxide or other insulator. Whereas the potential technological value of these materials is without question, what roles do the vacuum-Si and oxide-Si interfaces play? Is there anything interesting that has not already been discovered in the many years in which Si surfaces have been studied? We describe some interesting behaviors. Most important is the presence of strain and the essential instability of the very thin crystalline layer (called the template layer) resting on an oxide. Under appropriate conditions the template layer can dewet, agglomerate, and self-organize into an array of Si nanocrystals. Using LEEM, we observe this process and, with the help of first-principles total-energy calculations, we provide a quantitative understanding of this pattern formation and show how addition of Ge affects the energies and hence the pattern. We have been able to image the surface of SOI with STM, providing insights into the surface structure. Growth of heteroepitaxial films on SOI brings with it unique defect generation mechanisms that are associated with the Si-oxide interface, and a bending of the template that is counterintuitive. We fabricate thin membranes and free-standing structures to investigate the effect of added uniaxial stress on adatom diffusion and the nucleation and coarsening of 2D and 3D structures on this surface. Aspects of the work are supported by NSF, DARPA, ONR, and DOE.