The scaling of the complimentary metal oxide semiconductor (CMOS) technology requires the replacement of silicon dioxide with a high dielectric constant (high-k) material as a gate dielectric. Having a high-k film in the gate stack results in a capacitance equivalent to a much thinner film of a dielectric with a lower dielectric constant. The benefits of a high-k material are thus twofold, a higher capacitance results in a higher saturation current and improves the performance, and the increased thickness cuts down the gate leakage current and improves the power consumption. Successful implementation of a high-k dielectric in CMOS depends upon our ability to control the interfacial properties. The chemistry at the Si/dielectric and dielectric/electrode interfaces is determined by atomic-scale interactions, which ultimately sum to yield the electrical properties such as the threshold voltage observed macroscopically. A rigorous attempt to predict and control the interface behavior, therefore, must be based on the atomic-scale characterization and first-principle calculations. In this talk I will review the recent theoretical work on the interfaces of high-k dielectrics with Si and metals, and in particular, the calculations of the band alignment at the interface. I will discuss relative advantages of amorphous vs crystalline oxides (including epitaxial oxides). A connection will be made to the device characteristics such as the threshold voltage by means of using the results of density functional calculations in TCAD simulations.