The aggressive dimensional and performance targets for future technology generations place severe demands on lithography, not only for feature size scaling but also pattern integrity, density, line edge roughness, and process control. Already today many process "tricks" are routinely employed to shrink the dimensions of lithographically-defined features, such as resist trim and sidewall image transfer, but there are limitations on the extendibility of such approaches. While the great potential of various so-called "next generation" lithography techniques has been well touted, these solutions are inherently complex, require new tooling infrastructure, and present throughput challenges. Self organizing materials offer an exciting prospect for overcoming many of these hurdles. The simplicity, reproducibility, and dimensional control inherent in self-assembling materials make them attractive for silicon nanofabrication. In the grandest vision, we might imagine integrated circuits that one day "organize themselves"-yielding the ultimate sizing and positional control, but this vision is still in the realm of science fiction. However, already today we can implement self-organizing materials for selective unit processes to complement or enhance conventional semiconductor processing. For instance, self-assembling polymer films provide an appealing alternative to photoresists for certain types of patterning at nanometer-scale dimensions. In particular, diblock copolymer thin films self assemble into uniform, densely-spaced nanometer-scale features over wafer-scale areas. These films are compatible with standard semiconductor fabrication processes, enabling their integration into device and circuit fabrication. Such self-organizing materials provide novel nanofabrication capabilities and may enable solutions to some challenges confronting integrated circuit fabrication.