The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO@sub 2@ as the gate insulator. The replacement of SiO@sub 2@ with a high dielectric constant (high-k) material allows for an increase in the physical thickness of the gate insulator, while maintaining a low equivalent oxide thickness (EOT) and low direct tunneling current. The high-k material of choice will likely be a deposited film, which makes the replacement of SiO@sub 2@, a thermally grown layer, even more challenging. Atomic layer deposition (ALD) is a well-controlled surface saturating process using gas-solid interactions to deposit thin films. The technique results in covalent bonding between the gaseous precursors and the surface bonding sites. ALD provides highly uniform layers and the possibility to deposit mixed oxides. We have observed that the starting surface is extremely important to deposit high quality films with ALD. The surface termination of the substrate affects the growth kinetics of high-k materials in terms of a growth inhibition time. Longer inhibition times have shown detrimental effects when depositing ultra-thin high-k layers, e.g. films are not fully closed. Our results show that the ideal starting surface for ALD is an OH-terminated silicon surface, which is readily achieved with a chemical oxide. In terms of scaling, the benefit of using a high-k material is compromised if a lower dielectric constant insulator is also present in the gate stack. In order to scale to EOT’s below 1 nm with a chemical oxide present, the thickness of the high-k material must be significantly reduced. As a result the tunneling current through the gate stack will increase. By optimizing the surface preparation, we have achieved sub-1 nm EOT’s while maintaining leakage currents below 1 A/cm2 at -1 volt. Poly-Si integration with high-k materials remains a challenge. The flexibility of ALD to deposit mixed oxides provides options to fabricate scalable Poly-Si/high-k gate stacks.