AVS 49th International Symposium
    Nanometer Structures Thursday Sessions
       Session NS-ThA

Paper NS-ThA7
Metal-Catalyzed Nanowires for Integrated Devices and Interconnections

Thursday, November 7, 2002, 4:00 pm, Room C-207

Session: Nanowires
Presenter: T.I. Kamins, Hewlett-Packard Laboratories
Authors: T.I. Kamins, Hewlett-Packard Laboratories
X. Li, Hewlett-Packard Laboratories
T. Ha, Hewlett-Packard Laboratories
R.S. Williams, Hewlett-Packard Laboratories
Correspondent: Click to Email
As integrated-circuit technology progresses, interconnections between active devices become more important in determining overall circuit and system density and performance. Without special circuit techniques, interconnection delays can degrade circuit performance even if the device speed improves. Defining multiple levels of fine wires by conventional lithography becomes increasingly difficult as dimensions decrease, and defining wires by advanced techniques becomes attractive. Wires can be formed at the nanoscale by nanoimprint lithography or by self-assembly techniques such as anisotropic lattice-mismatched epitaxy or metal-catalyzed nanowire growth. The latter is especially attractive because the surfaces are formed by growth, rather than by etching, which can cause crystal damage. The catalyzing nanoparticles can be in the liquid phase or possibly in the solid phase during growth. Nanowires formed by self assembly can be used as interconnections between devices, and devices can also be formed within the nanowires, allowing close integration of the nanowires and devices. If the nanowire is uniformly doped, tradeoffs must be made between the series resistance in the interconnection and the ability to deplete the wire in the device region, limiting performance. Requiring the maximum depletion region to be at least half the wire diameter limits the conductance of the interconnection, and therefore the charging time of the device, to possibly unacceptable values. If portions of the wire can be selectively doped, the interconnecting region and the device can be separately optimized.