The aggressive scaling of the semiconductor technology continues relentlessly in order to satisfy the performance roadmap expectations created by "Moore's Law". The scaling of the planar CMOS transistor has been central to achieving past performance gains and remains as the main approach to realize the performance roadmap for at least the next decade. Concerns have been raised however, about the extendibility of this "evolutionary" approach because of the many integration, power and reliability challenges posed by the required use of exotic materials and extreme dimensional reductions. A number of companies and research institutions are looking into possible alternatives ranging from dual gate and FINFET transistors which still look & feel like CMOS devices, to more speculative and exotic solutions including quantum devices, molecular & organic transistors, novel non-volatile memory schemes, and carbon nanotube devices. Limited information exists on the reliability of such devices. This paper will discuss some of the key learnings reported, as well as speculate over the likely failure modes & mechanisms present for the more exotic configurations based on the extensive learning accumulated on the present planar CMOS devices and associated materials.