Integrated Circuit (IC) scaling per Moore’s Law has been the cornerstone for IC industry growth for the last 35 years. Based on the projections in the International Technology Roadmap for Semiconductors (ITRS), we will examine the MOSFET scaling envisioned to sustain Moore’s law for the next 15 years, during which the current MOSFET physical gate length of about 65 nm is expected to be scaled to about 9 nm. Issues discussed include the scaling of MOSFET performance, leakage, and power dissipation, as well as key innovations to enable the scaling. These include the potential utilization of high-k gate dielectrics, metal gate electrodes, and innovative source/drain (S/D) techniques such as raised S/D. Also, in the later stages of the ITRS, non-conventional, non-planar CMOS devices such as ultra-thin-body, fully depleted, double-gate MOSFETs may be utilized to overcome the limitations of conventional planar bulk CMOS transistors when the physical gate length is scaled to 25 nm or less.