AVS 49th International Symposium
    Electronic Materials and Devices Tuesday Sessions
       Session EL+SC-TuM

Paper EL+SC-TuM11
Effects of Interface Properties on Degradation and Reliability of CMOS Devices with RPECVD Stacked Oxide/Nitride and Oxynitride Dielectrics

Tuesday, November 5, 2002, 11:40 am, Room C-107

Session: Heterojunctions
Presenter: Y. Lee, North Carolina State University
Authors: G. Lucovsky, North Carolina State University
Y. Lee, North Carolina State University
Y. Wu, Advanced Micro Devices
C. Bae, North Carolina State University
J.G. Hong, North Carolina State University
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The effects of interface properties on device degradation and reliability of sub-2nm stacked oxide/nitride and oxynitride gate dielectrics prepared by the remote plasma enhanced CVD (RPECVD) technique under constant voltage stress (CVS) are investigated. Time evolutions of the transient SILC effect and threshold voltage (Vt) changes have been demonstrated to illustrate the breakdown behaviors and charge trapping during stress. More negative Vt shifts were observed for both P- and N-MOS devices, indicating the increases of hole trapping at the Si/SiO@sub 2@ interface. The p-channel transistors with stacked gate dielectrics received interface N@sub 2@/He nitridation and effectively suppress positive off-state leakage current, resulting in less device degradation as compared to the transistors without interface nitridation. This improvement is attributed to approximately one monolayer of N at the Si/SiO@sub 2@ interface which suppresses hole trapping. In addition, the influence of remote-plasma-assisted oxidation (RPAO) thickness on oxynitride device degradation and reliability is also studied. It is found that the devices with 0.6 nm RPAO exhibit improved C-V characteristics, lower post-breakdown current and higher TDDB reliability compared to the devices with 0.8 nm RPAO. The generation of interface states and the correlation between carrier conduction mechanism and TDDB are also discussed.