The integration of new high-k gate dielectric materials into advanced planar CMOS technology presents several significant challenges.@footnote 1@ Moreover, the introduction of these materials is expected to occur at an unprecedented pace to meet industry technology forecasts@footnote 2@ and will therefore mandate a rapid correlation of physical characterization with electrical performance. Although recent research has dwelled on the search for a material that yields a suitable (higher) dielectric constant, a more important problem is the actual integration of any new dielectric material in existing CMOS flows in a cost-effective manner. These integration issues include etching, control of phase segregation, dopant penetration, gate electrode compatibility, and many others that will influence the resultant electrical properties. This talk will examine several of these integration issues and the associated surface and thin film characterization challenges that must be addressed for successful high-k gate dielectric integration. @FootnoteText@ @footnote 1@For a review, see: G.D.Wilk, R.M.Wallace and J.M.Anthony, J. Appl. Phys. 89 (2001) 5243.@footnote 2@See the International Technology Roadmap for Semiconductors at http://public.itrs.net/.