Operation of integrated magnetoresistive nonvolatile latch cell memory using spin dependent tunneling (SDT) junctions has been demonstrated. These SDT devices were fabricated on top of commercially processed CMOS silicon circuit wafers. Fabrication of these devices presents many challenges to thin film deposition process developers. Process temperature compatibility and surface roughness are prime examples. In spite of these and other technical challenges, there is significant motivation to continue developing SDT fabrication processes. In particular, SDT devices provide resistance changes on the order of 50% (large signal), a wide range of resistance values (for low power applications), and magnetic switching speeds beyond 1 GHz. Furthermore, the SDT cell density is potentially competitive with commercial SRAM and DRAM. Recent success in SDT integrated device fabrication has been a result of using new approaches to surface preparation. Specifically, chemical mechanical polishing (CMP) has been employed to create a sufficiently smooth surface for SDT deposition. In-process atomic force microscopy (AFM) measurements suggest that a pre-deposition RMS substrate roughness of 0.2 nm is sufficient to allow successful SDT fabrication. This paper will discuss device-specific process details of SDT latch cells and their impact on the potential for near-term commercialization.