Magnetoresistive Random Access Memory (MRAM) has the potential to be a high-speed, low-voltage, high-density, nonvolatile solid state memory. MRAM is based on magnetic memory elements integrated in a backend process with standard CMOS semiconductor circuitry. Key attributes of MRAM technology are nonvolatility and unlimited read/write endurance. Our bit architecture is based on a minimum-sized active transistor as the isolation device in conjunction with a magnetic tunnel junction element (MTJ) defining the MRAM bit. Our MTJ material stack is composed of two magnetic layers separated by a thin dielectric barrier with the polarization of one of the magnetic layers pinned in a fixed direction. The resistance of the memory bit is either low or high dependent on the relative polarization, parallel or anti-parallel, of the free layer with respect to the pinned layer. In this talk we will summarize our progress on MRAM based on MTJ integrated with CMOS circuitry. We have demonstrated MTJ material in the 10 kOhms-um^2 range with MR values up to 50 %. The MRAM module is inserted in the back-end-of-line (BEOL) interconnect using four additional lithography steps. The source and isolation are shared between neighboring cells to minimize cell area. In this particular architecture, the cell size is 7.2um^2, corresponding to 9f^2, where f is one-half the metal pitch. We have developed a 256kb (16k x 16) MRAM memory based on 0.6 um CMOS with a 1T1MTJ (one transistor and one MTJ) cell. Nonvolatile data storage and read cycle times of 35 ns have been demonstrated. Read power consumption at 3.0V and 20MHz is about 24mW. These results show that MRAM based on MTJ has the potential to be a competitive memory with the attributes of high-speed read and write, as well as nonvolatility. The progress, potential and challenges of MRAM technology will be discussed. @FootnoteText@ This work in funded in part by DARPA.