IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Electronics Tuesday Sessions
       Session EL-TuP

Paper EL-TuP32
Formation of Titanium Silicides on Silicon-on-Insulator Wafers

Tuesday, October 30, 2001, 5:30 pm, Room 134/135

Session: Electronic Materials Poster Session
Presenter: C.H. Liu, National Tsing Hua University, Taiwan, R.O.C.
Authors: C.H. Liu, National Tsing Hua University, Taiwan, R.O.C.
C.J. Tsai, National Tsing Hua University, Taiwan, R.O.C.
L.J. Chen, National Tsing Hua University, Taiwan, R.O.C.
Correspondent: Click to Email
With continuing reduction of device feature size and increase of electronic component density in integrated circuit (IC) technology, SOI (silicon-on-insulator) is going to be the future substrate frame. The conventional advantages arising from SOI device structure and physics are high-speed operation due to low junction capacitance, no latch-up due to dielectric isolation, improved soft-error due to small junction area, reduced power consumption, harsh environment tolerance, and simplified fabrication process. As the CMOS device feature size scales down, formation of low resistivity silicides becomes increasingly difficult. Motivated by the effects of stress state of the metal-silicon diffusion couple on the silicide formation, especially on the silicon surface in SOI material, the influence of stress on silicide formation has been investigated. The SOI wafers used are separation by implantation of oxygen (SIMOX) wafers with a 1900-Å-thick buried oxide (BOX) layer located between the top silicon layer (with variant thickness range 1000~3000 Å) and bottom substrate. The in-situ stresses during reactions, with 5 °C/min ramping rate at 2~5 x 10@super -6@torr, were measured by a scanning laser beam reflection technique. Tensile stress was induced in the top silicon layer. The stress was found to increase with thinner silicon layer. The change is attributed to the difference in the thermal expansion coefficient between SiO@sub 2@ and Si. For the interfacial reactions of Ti on top silicon layer, the C49 to C54 TiSi@sub 2@ phase transformation on SOI wafers was found to be enhanced. The results are discussed in term of the variation of diffusivity of reacting species with the multi-layer stress state.