IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Electronics Tuesday Sessions
       Session EL-TuP

Paper EL-TuP26
Near-zero-thickness Molecular-layer Diffusion-barriers for Interconnect Applications

Tuesday, October 30, 2001, 5:30 pm, Room 134/135

Session: Electronic Materials Poster Session
Presenter: G. Ramanath, Rensselaer Polytechnic Institute
Authors: G. Ramanath, Rensselaer Polytechnic Institute
K. Chanda, Rensselaer Polytechnic Institute
X. Guo, Rensselaer Polytechnic Institute
M. Stukowski, Rensselaer Polytechnic Institute
S. Nitta, IBM Microelectronics
Correspondent: Click to Email

Ultrathin diffusion barriers that can conformally coat sub-100-nm-diameter vias--to allow a greater via fraction for low resistivity Cu--are necessary to fully realize the full potential of Cu technology. Here, we demonstrate the use of <2-nm-thick self-assembled molecular layers (SAMs) as effective barriers to Cu diffusion into SiO@sub 2@. Cu/SiO@sub 2@/Si(001) metal-oxide-semiconductor (MOS) capacitors, with and without SAMs at the Cu/SiO@sub 2@ interface, were investigated during bias-thermal annealing at temperatures between 100-300 °C in a 2 MV/cm electrical field. Capacitance-voltage and current-voltage measurements of MOS capacitors with SAMs having aromatic terminal groups consistently show as much as 5 orders of magnitude lower leakage currents and a factor of 4 higher mean-time-to-failure when compared with the corresponding values measured from uncoated samples. SAMs with short tail lengths or aliphatic terminal groups are ineffective in hindering copper diffusion, suggesting that molecular length and chemical configuration are key factors in determining the efficacy of SAMs as barriers. In addition to the temperature dependence of the barrier properties of SAMs, we will also present preliminary results pertaining to their deposition and behavior on SiLK. Our results will be discussed in the context of microelectronics device processing and integration, to evaluate the utility of ultrathin molecular layers in future interconnect structures.