IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Electronics Tuesday Sessions
       Session EL-TuP

Paper EL-TuP14
A Study of Iron-Contaminated p-type Silicon by Scanning Probe Microscopy

Tuesday, October 30, 2001, 5:30 pm, Room 134/135

Session: Electronic Materials Poster Session
Presenter: M.N. Chang, National Nano Device Laboratories, Taiwan, R. O. C.
Authors: M.N. Chang, National Nano Device Laboratories, Taiwan, R. O. C.
T.Y. Chang, National Chiao Tung University, Taiwan, R. O. C.
C.Y. Chen, National Nano Device Laboratories, Taiwan, R. O. C.
F.M. Pan, National Nano Device Laboratories, Taiwan, R. O. C.
B.W. Wu, National Nano Device Laboratories, Taiwan, R. O. C.
T.F. Lei, National Chiao Tung University, Taiwan, R. O. C.
Correspondent: Click to Email
One significant factor that degrades a Si device's performance and its yield is metallic contamination. Among the metallic contaminants, Fe has been the most extensively studied, because it is commonly observed as a dissolved impurity in Si wafers and, in comparison with other metallic contaminants, is more difficult to getter. In addition, it is also hard to observe the micro-distribution of oxidation related defects induced by slightly Fe contamination. In this work, we have employed scanning probe microscopy to investigate the distribution of oxidation related defects in the Fe-contaminated p-type Si wafers, on which a thermal oxide layer of 40 Å was grown. All of the p-type Si wafers was contaminated by a nitrate solution of a low Fe contaminant concentration, simulating the influence of Fe contamination during the cleaning process. From scanning capacitance microscopy (SCM) studies on the 10-ppm Fe-contaminated samples, a defect region exhibits a lower dC/dV signal than the surrounding normal area at a low bias voltage. According to contact-mode atomic force microscopy (AFM), the surface morphology has little effect on the SCM signal. This is attributed to the positive trapped charges (PTC), which are closely related to negative shift in the flat band voltage and affect the dC/dV value. In the defect region, two small areas about 0.1 µm in size have the lowest SCM signal, suggesting that these two areas have the highest PTC density. One can expect that these two areas would be the most likely weak points, where significant current leakage and oxide breakdown can occur at a high gate bias. When the contaminant concentration is increased, SCM observed more PTC regions.These results imply that SCM is capable of detecting the position of weak spots in silicon wafers, which may lead to leakage and breakdown problems in gate oxide.