IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Electronics Friday Sessions
       Session EL-FrM

Paper EL-FrM9
Comparison of TiN, TaN, and WN@sub x@ as Diffusion Barriers for Copper on Silicon Dioxide: Thermal Annealing and Bias Temperature Stress Tests

Friday, November 2, 2001, 11:00 am, Room 124

Session: ULSI Metallization & Interconnects
Presenter: C.O. Steinbrüchel, RPI
Authors: H. Kizil, RPI
C.O. Steinbrüchel, RPI
Correspondent: Click to Email
The stability of TiN, TaN, and WN@sub x@ as diffusion barriers for Cu on silicon dioxide has been investigated using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements as a function of thermal annealing and bias temperature stress (BTS) conditions. Samples consisted of MOS capacitors with a film stack of 300 nm Cu/barrier/25 nm thermal silicon dioxide on Si. The barrier thickness was 5, 10, or 20 nm. The WN@sub x@ was investigated at two different compositions. Compositional depth profiles were taken with XPS and SIMS. Samples were pre-annealed in Ar/3% hydrogen for 30 minutes at various temperatures. BTS tests were performed at 2 MV/cm and 150, 200, and 250 °C, for periods of up to one hour in flowing nitrogen. The main results can be summarized as follows: In order for BTS to yield negligible C-V flat-band voltage shifts, pre-annealing at 350 °C is necessary. This produces a substantial number of initial leakage current failures (i.e. before BTS) with TiN, but not with the other barrier materials. The leakage current in I-V tests is a much better test for barrier integrity than the flat-band voltage shift (or the absence thereof), in the sense that samples with minimal shifts in the C-V plots may still give unacceptably high leakage currents. TaN and WN@sub x@ consistently behave better than TiN under all stress conditions. The effect of oxygen in the barrier and at the Cu/barrier interface is also discussed.