AVS 47th International Symposium
    Thin Films Tuesday Sessions
       Session TF-TuA

Paper TF-TuA4
Tungsten Silicide (WSi2) for the Alternate Gate Metal in Metal-Oxide-Semiconductor (MOS) Devices

Tuesday, October 3, 2000, 3:00 pm, Room 203

Session: Mechanical Properties of Thin Films
Presenter: K. Roh, Sungkyunkwan University, Korea
Authors: K. Roh, Sungkyunkwan University, Korea
S. Youn, Sungkyunkwan University, Korea
S. Yang, Sungkyunkwan University, Korea
Y. Roh, Sungkyunkwan University, Korea
Correspondent: Click to Email
Recently, it has been recognized that both achieving low gate resistance and suppressing poly-Si gate depletion are key factors for developing deep submicron MOSFETs. In the present work, tungsten silicide (WSi2) deposited directly on SiO2 is proposed for the alternate gate electrode for deep-submicron MOSFETs. PMOS capacitors were fabricated on 4~7@ohm@-cm, (100) n-type Si wafers. Thermal oxidation of the Si was carried out at 850°C for 80 s using RTP to grow ~110Å SiO2. WSi2 were then deposited directly on SiO2 in a cold-wall LPCVD system: Deposition temperature and pressure were 350°C and 0.7Torr, respectively. The ratio of SiH4/WF6 flow was changed from 40 to 70. RTP was used for post-deposition annealing at various conditions. Detailed analysis of mechanical properties of WSi2 deposited on SiO2 reveals that a low resistivity can be obtained while satisfying the requirement for the low thermal budget. In addition, HTEM results showed that WSi2-SiO2 interface remains very flat after annealing as-deposited WSi2 films using RTP at 780°C in vacuum. Since F diffusion into SiO2 during the WSi2 deposition and annealing steps has been known to cause the irregular formation of WSi2-SiO2 interface, we attribute the current results to the indirect evidence of negligible F diffusion. In addition, the electrical characteristics of annealed WSi2-SiO2-Si (MOS) capacitors were also improved in view of charge trapping. For example, oxide charging curves monitorted during Fowler-Nordheim tunnel electron injection indicate that the shift of flatband voltage is less for RTP annealed samples as compared to that of as-deposited samples. The phenomenon of gate depletion which has been a serious problem of poly-Si gate is also suppressed in the WSi2 gated MOS capacitors. The C-V data shifted to the positive gate bias after annealing, and we interpret that this positive shift is caused by the workfunction difference that may be caused by the change of Si to W ratio due to the annealing process.