AVS 47th International Symposium
    Dielectrics Thursday Sessions
       Session DI+EL+MS-ThM

Paper DI+EL+MS-ThM6
Studies on Accurate Determination of the Physical Thickness of nm Gate Oxides and its Correlation with the Electric Thickness

Thursday, October 5, 2000, 10:00 am, Room 312

Session: Ultrathin Dielectrics and Interfaces
Presenter: D.W. Moon, Korea Research Institute of Standards and Science
Authors: D.W. Moon, Korea Research Institute of Standards and Science
H.K. Kim, Korea Research Institute of Standards and Science
H.J. Lee, Korea Research Institute of Standards and Science
H.M. Jo, Korea Research Institute of Standards and Science
H.S. Jang, Kwangju Institute of Science and Technology, Korea
H. Hwang, Kwangju Institute of Science and Technology, Korea
Correspondent: Click to Email
Accurate Determination of nm gate oxides is critical for the development of nanoelectronic devices as well as for CMOS device scaling beyond 100 nm. In semiconductor industries, the thickness of gate oxides has been measured by ellipsometry. However, the accuracy has been not evaluated especially for gate oxides thinner than 10 nm. Recently, TEM and spectrometric ellipsometry(SE) have been used to measure the physical thickness of nm gate oxides and the electric methods such as I-V an C-V have been modified to include quantum effects. In this work, to estimate the uncertainty and improve the accuracy of the methods used for gate oxides thickness determination, TEM, SE and Medium Energy Ion Scattering Spectroscopy(MEIS) were used to determined the physical thickness of 6 gate oxides from 9 nm thick to 1.5 nm native oxide thick. MEIS can analyze the composition and structure of ultrathin films with atomic layer depth resolution. It was investigated that MEIS can be a reference for gate oxide thickness determination down to 1-2 nm. The difference of the physical thickness determined with TEM, SE and MEIS were discussed and compared with the electric thickness determined by I-V and C-V methods. For the gate oxides studied, the thickness determined by the Si MEIS peak was 1.5 nm thicker than that by the O MEIS peak. The thickness determined by SE and TEM was between the two values, while SE gave ~0.5 nm higher thickness than TEM. However, with the interlayer thickness, TEM thickness approached that of Si MEIS peak thickness. The electric thickness determined with I-V and C-V was close to that of Si MEIS peak thickness within 0.2nm. The thickness by SE is quite sensitive to the refractive index value used for fitting, especially for gate oxides thinner than 5nm. Based on this multi-disciplinary approach, it will be discussed how to provide standards for nm gate oxides approaching the limit of CMOS and how to transfer the standards to SE which is widely used in semiconductor process lines.