AVS 47th International Symposium
    Dielectrics Thursday Sessions
       Session DI+EL+MS-ThA

Paper DI+EL+MS-ThA8
High Temperature Etch Processing for FeRAM MFM Capacitor Stack Fabrication

Thursday, October 5, 2000, 4:20 pm, Room 312

Session: High K Dielectrics: Perovskites
Presenter: L.G. Jerde, Tegal Corporation
Authors: L.G. Jerde, Tegal Corporation
A. Cofer, Tegal Corporation
R.A. Ditizio, Tegal Corporation
S. Marks, Tegal Corporation
J.A. Meyer, Tegal Corporation
K.A. Olson, Tegal Corporation
S.P. DeOrnellas, Tegal Corporation
Correspondent: Click to Email
The unique materials utilized in FeRAM MFM capacitor stacks present numerous integrated device fabrication challenges, particularly in the patterning of these materials and the capacitor stacks that utilize them. Many of these patterning challenges are due to the intrinsic involatility of the reaction products formed when etching the elemental constituents of the FeRAM materials (i.e., Pt, Ir, Pb, Zr, Sr and Bi). These challenges have been successfully met for several years by utilizing photoresist etch masks in conjunction with the plasma etch technologies of low pressure, high density and dual frequency. While this technological approach is extendible for the foreseeable future of FeRAM capacitor stack definition, the intrinsic involatility of their etch reaction products has recently sparked wide spread interest in utilizing high temperature etch processes to meet the as yet undefined future requirements for these applications. Although there are benefits to this high temperature approach, there are also risks. Among these risks are a number of key considerations that must be dealt with to successfully develop and implement high temperature etch process solutions for FeRAM applications. The first set of these considerations is related to the requirement that the etch tool provides reliable wafer, as opposed to wafer chuck, temperature and temperature uniformity control. In view of the industry trend toward single mask, full stack processes, another set of considerations is the requirement that the etch tool be able to rapidly vary the wafer temperature to accommodate the optimum temperature for each of the FeRAM materials being used. Yet another set of considerations are those related to wafer temperature limitations imposed by the Perovskite structure transition temperature, device damage and thermal budget. We will discuss and illustrate these considerations and present selected high temperature etch process results for various FeRAM films and stacks.