Each year, IC manufacturers invest billions of dollars in new equipment in an attempt to increase their competitiveness by delivering enhanced performance and more functionality at a lower cost. Success in today’s marketplace requires successful technology integration under increasing market pressure to deliver products as quickly as possible. Unfortunately, standard yield improvement practices focus too narrowly on defect elimination and use techniques that solve yesterday’s not today’s problems a comprehensive view of yield learning. To ensure profitability, a new approach to yield learning must be developed. Inevitably, these changes require a re-defining of the interfaces between design, test and manufacturing. In this paper, we present a comprehensive view of the yield problem and a "holistic" yield ramping methodology specifically designed to significantly reduce the yield ramp time by eliminating not only defects, but also by resolving parametric and systematic problems. Manufacturing defect data, process recipe, and design information are analyzed simultaneously, to derive a much deeper understanding and subsequent solution to the process and design architecture issues that affect yield and performance. In combination with the use of simulation and a hypothesis-driven work style, this approach delivers increased yield and performance in a fraction of the time required by traditional methods.