AVS 46th International Symposium
    Electronic Materials and Processing Division Thursday Sessions
       Session EM2-ThA

Paper EM2-ThA6
Deposition of Yttrium Oxide by Yttrium Sputter/Thermal Oxidation and Reactive Sputtering for Advanced High k Gate Dielectrics

Thursday, October 28, 1999, 3:40 pm, Room 611

Session: Silicon Carbide and Dielectrics on Si
Presenter: J.J. Chambers, North Carolina State University
Authors: J.J. Chambers, North Carolina State University
G.N. Parsons, North Carolina State University
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The advent of 50nm MOSFET devices will require an equivalent SiO@sub 2@ thickness (t@sub ox,eq@) of 10Å. Direct tunneling through SiO@sub 2@ becomes problematic below about 15Å. To maintain low tunneling, the gate thickness must be >15Å, which requires an insulator with k>3.9. We form yttrium oxide on Si by: 1) yttrium sputtering followed by thermal oxidation; and 2) reactive sputtering of yttrium. Conditions for the sputter/thermal oxidation process were yttrium sputter in 4.3mTorr Ar at 25°C then ex-situ furnace oxidation in 1 atm N@sub 2@/O@sub 2@ at 900°C. Conditions for reactive sputtering of yttrium were 4.3mTorr, 25-500°C and an Ar/N@sub 2@O flow ratio of 0.5. Infrared absorption peaks from 400-600cm@super -1@ are present in the FTIR transmission spectra of the sputter/thermal oxidation and reactive sputtered films. These peaks are consistent with the 467, 562 and 698cm@super -1@ absorption peaks present in the spectrum of a 99.9% pure Y@sub 2@O@sub 3@ standard. CV and IV electrical measurements have been performed on films from both processes. Leakage current at 2V of 0.1µA/cm@super 2@ has been measured for sputter/thermal oxidation (t@sub ox,eq@=50Å) and reactive sputtered (t@sub ox,eq@=100Å) films. Using optical thickness measured with spectroscopic ellipsometry, effective dielectric constants are approximately 8.0 for films from both processes. Bulk Y@sub 2@O@sub 3@ has k=14-17, which suggests that the films described here have a reduced k in their thin film form, some yttrium silicate formation and/or an underlying SiO@sub 2@ layer. Under some deposition conditions, inert gas annealing increased inversion capacitance in the CV trace, possibly due to interfacial silicide formation. We will discuss the affects of pre-deposition N@sub 2@ and N@sub 2@O plasma surface treatments on the electrical properties of these films. The chemical and structural changes upon annealing will be investigated using XPS, AFM and RHEED.