AVS 46th International Symposium
    Electronic Materials and Processing Division Thursday Sessions
       Session EM1-ThM

Paper EM1-ThM6
The Stability of Thin TiN and TaN Layers as Diffusion Barriers for Copper under Thermal Annealing and Bias Temperature Stress Conditions

Thursday, October 28, 1999, 10:00 am, Room 608

Session: Cu, Low-k Dielectrics and Interfaces
Presenter: C. Steinbrüchel, Rensselaer Polytechnic Institute
Authors: H. Kizil, Rensselaer Polytechnic Institute
G. Kim, Rensselaer Polytechnic Institute
C. Steinbrüchel, Rensselaer Polytechnic Institute
B. Zhao, Conexant Systems
L. Tsau, Conexant Systems
M. Brongo, Conexant Systems
Correspondent: Click to Email
The stability of TiN and TaN as diffusion barriers for Cu has been investigated using capacitance-vs-voltage (C-V) and leakage current-vs- voltage (I-V) measurements as a function of thermal annealing and bias temperature stress (BTS) conditions. Samples consisted of MOS capacitors with a film stack of 300 nm Cu/barrier/25 nm thermal silicon dioxide on Si. The barrier thickness was 5, 10, or 20 nm. Samples were pre-annealed in Ar/3% hydrogen for 30 minutes at various temperatures. BTS treatments were performed at 2 MV/cm and 250 C, 2 MV/cm and 200 C, and at 1.5 MV/cm and 250 C, for periods of up to one hour in flowing nitrogen. The main results can be summarized as follows: In order for BTS to yield negligible flat-band voltage shifts, pre-annealing at 350 C is necessary. This produces a substantial number of initial leakage current failures (i.e. before BTS) with TiN but not with TaN. BTS of samples pre-annealed at lower temperatures causes significant shifts in the C-V plots. However, the flat-band voltage shift (or the absence thereof) is not a very good indicator of barrier stability, in the sense that samples with minimal shifts in the C-V plots may still give unacceptably high leakage currents. TaN consistently behaves better than TiN under all stress conditions.