Advanced IC interconnect structures incorporate damascene patterning (in-laid metal) to improve packing density and reduce manufacturing cost. Chemical-Mechanical Planarization (CMP) of copper or aluminum is used to delineate the trenches and/or vias after dielectric etching and metal deposition. The Damascene patterning process is presented, with an emphasis on CMP issues. The role of the metallic liner and the interlevel dielectric (ILD) are highlighted, the effect of alternative CMP consumables (slurries and pads) discussed, and the interaction between the CMP process and post-CMP cleaning in establishing a robust manufacturing capability presented. Examples used to highlight these issues will include dual Damascene patterned copper interconnects with polymer ILDs and tantalum liners and single Damascene patterned copper and aluminum interconnects with oxide ILDs and magnetic liners. The possibility of scaled copper interconnects without conventional conducting liners will be presented.