AVS 46th International Symposium
    Electronic Materials and Processing Division Wednesday Sessions
       Session EM-WeP

Paper EM-WeP2
Study of the Impact of Time-Delay Effect on the Critical Dimension of Tugnsten Silicide/Polysilicon Gate After Reactive Ion Etching

Wednesday, October 27, 1999, 5:30 pm, Room 4C

Session: Poster Session
Presenter: S. Lee, Winbond Electronics Corporation, Taiwan
Authors: S.P. Lin, Winbond Electronics Corporation, Taiwan
C.H. Ou, Winbond Electronics Corporation, Taiwan
S. Lee, Winbond Electronics Corporation, Taiwan
Y.C. Tien, Winbond Electronics Corporation, Taiwan
C.F. Hsu, Winbond Electronics Corporation, Taiwan
Correspondent: Click to Email
In the fabrication of submicron devices with high-density integration, the control of critical dimension (CD) of tungsten silicide/polysilicon gate becomes extremely crucial in device performance. To ensure a reliable gate patterning process, etching recipe with a very high selectivity is used to control the gate profile to be notching-free and vertical as well as keeping the gate oxide loss minimized. Besides the use of oxygen and chlorine-based chemistry in gate stack etching, HBr is also used to improve the selectivity of polysilicon to gate oxide. As a consequence of high selectivity, polymer residues become a major factor in CD control. It is believed that the presence of HBr in the plasma is responsible for polymer formation. HBr and its polymer residues may induce surface reactions to form thin oxide layers. Such a phenomenon has been observed if the wafers are not treated with HF vapor (for the removal of polymer residue) immediately after reactive ion etching (RIE) of the gate. The magnitude of the oxide film growth is proportional to the time delayed between RIE and HF vapor treatment. The sidewall thickness of the gate is also affected by the time-delay effect. The growth of oxide film on sidewalls can eventually affect the gate CD and thus the device performance. A simple reaction model for the growth of oxide film is proposed to explain the correlation between delayed time, CD bias, and product yield.