AVS 46th International Symposium
    Electronic Materials and Processing Division Tuesday Sessions
       Session EM-TuA

Paper EM-TuA8
Thermally Grown Gate Insulators for Heterostructure p-MOSFETs

Tuesday, October 26, 1999, 4:20 pm, Room 608

Session: High Dielectric Constant Materials and Thin Oxides
Presenter: D.W. Greve, Carnegie Mellon University
Authors: D.W. Greve, Carnegie Mellon University
A.C. Mocuta, Carnegie Mellon University
Correspondent: Click to Email
With decreasing channel length and increasing channel electric field, it is increasingly difficult to maintain adequate transistor ON currents in scaled MOS technologies. Germanium-silicon heterostructure p-MOSFETs potentially offer improvements in channel mobility of 30-50%; however, devices with thick channels and high germanium fraction may relax during thermal oxidation or other subsequent high-temperature processing. We have fabricated heterostructure MOSFETs and MOS capacitors using germanium-silicon-carbon epitaxial layers grown by UHV/CVD. We will show that low-carbon Si@sub 1-x-y@Ge@sub x@C@sub y@ channels do not relax for thermal anneals as high as 900 C. Consequently it is possible to use a thermally grown gate SiO@sub 2@ gate insulator while still maintaining a high channel charge capacity in the Si@sub 1-x-y@Ge@sub x@C@sub y@ layer. This has been demonstrated using heterostructure MOS capacitors with 30 nm Si@sub 1-x-0.002@Ge@sub x@C@sub 0.002@channels in which the germanium fraction x has been linearly graded from x=10% to x=40%. For cap layers approximately 6 nm in thickness after gate insulator growth, germanium surface segregation during epitaxial layer growth leads to a poor quality insulator-semiconductor interface. However, for thicker cap layers nearly ideal MOS C(V) characteristics are observed. We will also report on heterostructure p-MOSFETs which have been fabricated with Si@sub 1-x-y@Ge@sub x@C@sub y@ channels and thermally grown gate insulators. It will be shown that these devices exhibit channel mobilities of 200 cm@sup 2@/Vsec at room temperature, which is comparable to that reported with Si@sub 1-x@Ge@sub x@ channels and plasma silicon dioxide gate insulators. This demonstration opens the way toward the application of heterostructure p-MOSFETs in practical CMOS technologies.