AVS 46th International Symposium
    Electronic Materials and Processing Division Tuesday Sessions
       Session EM-TuA

Invited Paper EM-TuA5
High K Gate Dielectrics for Sub-100nm CMOS

Tuesday, October 26, 1999, 3:20 pm, Room 608

Session: High Dielectric Constant Materials and Thin Oxides
Presenter: D.L. Kwong, University of Texas, Austin
Correspondent: Click to Email
With the scaling down of device dimensions, conventional SiO2 and oxynitride films will reach their physical limits in terms of thinning. As a result, there has been a great interest in the development of high permittivity materials as MOS gate dielectrics for sub-100nm CMOS. In this talk, the requirements and significant challenges in developing high K gate dielectrics with performance and reliability specs consistent with NTRS roadmap are reviewed. Results will be presented to demonstrate the importance of the interface layer at highK/Si interface. The choice of high K materials and issues associated with process integration for sub-100nm CMOS will also be discussed.