AVS 45th International Symposium
    Thin Films Division Thursday Sessions
       Session TF-ThM

Paper TF-ThM7
Stability of Very Low Temperature Amorphous Silicon Thin Film Transistors on Flexible Plastic Substrates

Thursday, November 5, 1998, 10:20 am, Room 310

Session: Thin Films for Flat Panel Applications
Presenter: L.L. Smith, North Carolina State University
Authors: C.S. Yang, North Carolina State University
L.L. Smith, North Carolina State University
C.B. Arthur, North Carolina State University
G.N. Parsons, North Carolina State University
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Active matrix transistor arrays on transparent plastic substrates will enable new high resolution flexible and rugged large area electronic display systems, including liquid crystal displays (LCDs), and organic light emitting displays (OLEDs). Hydrogenated amorphous silicon thin film transistors (TFTs) for active matrix LCDs are currently formed on glass substrates using temperatures in excess of 250°C. Lower temperature processes are of interest for TFTs on plastics, but stability of low temperature TFTs has not been reported. In this presentation, we will describe low temperature (<125°C) plasma deposition processes for amorphous silicon and silicon nitride, including atomic force microscopy (AFM) analysis of substrate surfaces, nucleation, and film growth. We will also describe the fabrication of bottom gate inverted staggered TFTs on 7 mil (190 µm) polyethylene terephthalate (PET) substrates. Low-temperature devices showed linear mobilities >0.3 cm@super 2@/V-s and off currents <2x10@super -12@ A, with on/off ratios ~10@super 7@. We will also show results of stability tests under dc electrical stress, and compare the low T devices with conventional TFTs formed at higher temperatures. We find that when electrical stress (V@sub g@=25 V, V@sub sd@=10 V) is applied for 60 seconds to a device formed at 250°C, the threshold voltage on a I@sub d@ vs V@sub g@ plot shifts from 1.5 V to approximately 3.0 V. Upon negative applied gate bias, the drain current onset is observed to shift to more negative voltages, consistent with state creation in the amorphous silicon layer near the amorphous silicon/silicon nitride interface. For the device formed at 110°C, a larger initial threshold of 5.0 V is observed. However, after 60 s dc stress, the threshold shifts to 7.0 V, so that the change in threshold is similar for the two devices. These results indicate that amorphous silicon is a viable material for stable active matrix array electronics on low temperature plastic substrates.