Key goals driving FPD process development are: 1. large panel size; 2. Low cost; 3. Low power consumption. Recent introduction of new process technologies especially in the dry etch area are key enablers for new display architecture. Increase in display size with longer gate and data lines is driving the switch to aluminum metal with its lower resistivity to reduce the RC time delay. Hillock free Aluminum gate metal is enabled by tapered Al dry etching and high rate PECVD process with short time-temeprature cycle. Cost reduction has focused on productivity improvement but new 3rd generataion tools has renewed interest recently in reduced mask count display architecture. ITO pixel is etched using very strong acids and dictates its placement in the process architecture. New ITO dry etch removes process constraints and allows placement of the ITO on top of the passivation dielectric. Power consumption is dominated by backlight intensity and can be reduced by higher aperture ratio pixel design. The ITO pixel dimension is increased if the TFT size and its assoicated coupling capacitance is shrinked through the use of selective n+ etch in intrinsic silicon.