Invited Paper MS-TuM1
Reaction/Annealing Pathways for Forming Ultrathin Silicon Nitride Films for Composite Oxide-Nitride Gate Dielectrics with Nitrided Crystalline Silicon-Dielectric Interfaces for Application in Advanced CMOS Devices
Aggressive scaling of CMOS devices requires gate dielectrics with oxide equivalent thicknesses of ~1 nm by 2012. Direct tunneling is a limitation in FETs when oxide thicknesses are reduced to <2 nm. In addition, boron diffusion from p+ poly-Si gate electrodes in PMOS FETs leads to additional electrical problems for oxide thicknesses <4 nm. Interfacial nitridation improves reliability in NMOS FETs; however, it is not effective in PMOS FETs due to of boron pile-up at the Si-dielectric interface. One solution to these problems is the integration of composite oxide-nitride composites with nitrided interfaces; NON dielectrics, into CMOS devices. The paper discusses: i) deposition of hydrogenated silicon nitride by remote plasma-enhanced chemical-vapor deposition (RPECVD); ii) characterization of plasma-deposited nitrides by IR and AES; and iii) effects of post-deposition annealing on the bonded-H content. Formation of nitride thin films for NON composite dielectrics requires two process steps: i) deposition of a hydrogenated silicon nitride film at 300°C by RPECVD, followed by ii) rapid thermal annealing in an inert ambient at 900°C. During the anneal H-atoms are evolved from near-neighbor SiH and SiNH bonds, and the resulting Si and N-atom dangling bonds combine to form new SiN bonds accounting for the device-quality electrical performance. Electrical performance of devices with composite i) oxide-nitride-oxide, ONO, dielectrics, and ii) ON dielectrics with fully nitrided interfaces, NON, is discussed. For example, we demonstrate that approximately 2 molecular layers of nitride, ~0.8 nm, at the top surface of the NON dielectric is sufficient to stop B-penetration out of p+ poly-Si gate electrodes during dopant drive-in/activation anneals. Finally, nitrides produced by the two step process are qualitatively different from CVD nitrides deposited at higher temperatures, ~500°C, and subjected to post-deposition anneals in oxidizing ambients.