AVS 45th International Symposium
    Manufacturing Science and Technology Group Tuesday Sessions
       Session MS-TuA

Paper MS-TuA4
Low k Polymer Etching for Dual Damascene Technology Application to SILK Material

Tuesday, November 3, 1998, 3:00 pm, Room 317

Session: Process, Integration, and Modeling
Presenter: F. Vinet, LETI-GRESSI, France
Authors: F. Vinet, LETI-GRESSI, France
E. Tabouret, LETI-GRESSI, France
Ch. Vivensang, Tokyo Electron Europe LTD, France
Correspondent: Click to Email
Scaling down of interconnect requires a change in architecture and materials to be integrated. Dual Damascene scheme in combination with copper as metal conductor, appears to be the most acurate choice for sub 0.18 µm design rule technology. The dielectric material necessary for this application is still under improvement to achieve the required properties such as, dielectric constant<2, thermal stability and good adhesion on mineral or organic layers. The most advanced materials are based on polymers. In order to etch these materials, a hard mask is necessary due to their poor resist selectivity (1:1).Silicon dioxide (SiO2)is the most commonly used hard. Depending on the polymer composition, the compromise between high aspect ratio and mask erosion has to be found. Among the different available materials, SILK from Dow Chemicals, presents a chemical stability compatible with the thermal budget of our current technology. Moreover, this material is purely organic and contents no silicon; in this case an etching chemistry without fluorine can be used, ensuring a good selectivity to the hard mask. The etching properties, as well as the requirements related to the use of a Dual Damascene architecture have been investigated in this paper. A 1500Å thick SiO2 hard mask was deposited on top of 1µm spin coated SILK. By using DUV lithography 0.225 µm holes and 0.3/0.3 µm L/S patterns were defined. A medium density etcher from TEL, DRM85 UnityII was used for the experiments. By using a pure O2 chemistry, an overhang between hard mask and SILK is observed ; moreover due to isotropic etching, the sidewalls after etching are bowed. In order to overcome these effects, different chemistries have been tested in combination with etching process parameters to form a passivating layer. With optimised conditions, 0.225 µm holes were obtained with straight profiles. In our experiments, the limitation for higher aspect ratios is due to lithography and not to etching conditions. Whatever the Dual Damascene structure is used, successive steps of fluorinated and non fluorinated chemistry has to be used to etch alternatively SiO2/SILK/ SiO2.The effect of such a sequence has been studied on the etched profiles as well as the influence of reactor fluorine memory effect. Optimised conditions for both, process and reactor, are proposed to ensure a reliable process for sub 0.18µm technology.